Wireless RFIC Analog Circuit Design Engineer (PLL/XO)

MediaTek
📍 Hsinchu City, Taiwan Province, Taiwan 💼 Full-time 🕒 Posted June 21, 2026

Job Description

Job Description1. Wireless RFIC analog circuit design.
2. Frequency synthesizer, phase-locked loop, voltage-controlled oscillator, crystal oscillator design, frequency divider, etc.

#LI-DC3Requirement1. MS or above with major in EE or Telecommunication Engineering related field.
2. Familiar with operation principles of RF frequency synthesizer and phase-locked loop.
3. Excellent working attitude and good interpersonal and communication skills.

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Job Details

  • Location Hsinchu City, Taiwan Province
  • Job Type Full-time
  • Category Engineers
  • Posted Date June 21, 2026
  • Application Deadline July 31, 2026