Job Description
JOB DUTIES: In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management. Writes comprehensive electrical & functional test plans for the processor interface validation of processors. Executes electrical & functional test plans for client processors using hardware & software validation tools, oscilloscopes, & logic analyzers. Debug of electrical & functional issues for new processors. Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug processor validation.
EXPERIENCE AND EDUCATION:
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- Location San Jose, California
- Job Type Full-time
- Category Engineers
- Posted Date June 10, 2026
- Application Deadline July 20, 2026