Static Timing Analysis Manager, Full Chip, SOC, Implementation

Static Timing Analysis Manager, Full Chip, SOC, Implementation

_corporate_fare_ Google _place_ Mountain View, CA, USA

**Advanced**

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 10 years of experience with silicon implementation and chip integration.
+ Experience with STA sign-off constraint authoring for full-chip level, tapeout sign-off requirements, checklists, and associated automation.
+ 3 years of experience in people management, developing employees.
+ Experience delivering silicon.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ E...

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