Standard Cell Layout Design Engineer

**Company**:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
**Job Area**:Engineering Group, Engineering Group > ASICS Engineering
**General Summary**:
**Job Summary**:
**Job description**:
- Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as Cadence Virtuoso. This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization, and design efficiency.
- Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).
- Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.
- Maintain and manage layout databases using designated Design Management software.
- Engage with the engineering design team to understand design concepts, constraints, and proje...

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