Staff Layout Engineer

A highly autonomous engineering lead with 8–10 years of deep expertise in full-scale IC layout design and sign-off verification from cell level up to complex PHY/CHIP levels.

This role is defined by absolute technical independence, deep DRM expertise, and a mandate to innovate Best-Known Methods (BKMs) and project workflows.

Beyond technical mastery, this professional drives cross-functional team success by managing client and teams, complex tasks, challenging legacy workflows, mentoring talent, and executing post-mortems to ensure flawless silicon delivery.

End-to-End Layout & Physical Verification Sign-Off Unsupervised Hierarchical Execution: Autonomously design, implement, and verify layouts scaling seamlessly from unit cells and blocks up to complex MACRO, PHY, and full top-level CHIP integrations.

Rigorous Quality & Waiver Control: Independently run advanced physical verification flows, rigorously double-checking results, au...

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