STA Engineer

Job Title: STA Engineer Experience: 3+ Years
Domain: VLSI / ASIC Physical Design
Job Summary:
We are seeking a highly motivated Static Timing Analysis (STA) Engineer with 3+ years of experience in VLSI Physical Design and timing closure. The candidate will be responsible for performing block-level and full-chip STA, driving timing convergence, and ensuring successful signoff across all corners and modes.
Key Responsibilities:
Perform Static Timing Analysis (STA) at block and full-chip level
Drive timing closure for setup/hold violations
Handle MMMC / MCMM analysis across PVT corners
Create, review, and validate SDC constraints
Work on ECO implementation and timing validation
Perform timing signoff using industry-standard tools
Collaborate with RTL, Synthesis, and Physical Design teams
Analyze and debug timing issues including OCV/AOCV/POCV
Required Skills:
Hands-on experience with Synopsys PrimeTime or Cadence T...

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