Job Description
Job Description
Job Purpose:
• Lay out GaN power device according to design rules and to the standard required by designers.
• Deliver high quality, high yield layouts in agreed timescales.
Principal Accountabilities:
• Block and top level layout and verification using LVS, DRC, ERC and other required verification checks
• Layout work to be of highest standard and free from issues with device mismatch, electro migration, parasitic effects, latch up and ESD weakness.
• Manage and keep track layout schedule to ensure on time tape out
• Tape out database and document preparation
• Attendance at and participation in all relevant project meetings, keeping project manager aware of achievements, issues and potential risks to timescales.
• Demonstrates an ability to learn new tool features/procedure with little supervision and proactively share knowledge with peers.
Qualifications
【Must-have】 Submit your application today and join our talented team at Renesas Electronics.Ready to Apply?
Job Details
- Location Japan, Tokyo
- Job Type Full-time
- Category Engineers
- Posted Date June 26, 2026
- Application Deadline August 05, 2026