Sr Staff Engineer, Design Verification

Renesas Electronics

📍 Bengaluru, Karnataka, India 💼 Full-time 🕒 Posted June 08, 2026

Apply Now Similar Jobs

Job Description

Job Description
Job Responsibilities
Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) 
SoC Level verification is a must.
Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug.
Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits.
Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency.
Generate Verification Plan from the Specifications using vManager
Determine Coverage and design completeness requirements
Generate random-constraint tests to cover all customer-use-models
Create Assertions, cover-groups, checkers, monitors and automatic reporting
Set-up and run regression reports
Works diligently to accomplish project goals ...
            

Ready to Apply?

Submit your application today and join our talented team at Renesas Electronics.

Submit Application

Job Details

Location Bengaluru, Karnataka
Job Type Full-time
Category Engineers
Posted Date June 08, 2026
Application Deadline July 18, 2026