Job Description
SoC DFT Engineer
Job Description:
Scan insertion.
SCAN DRC/Coverage debug.
ATPG Pattern generation.
Gate level simulations ( Zero delay/Timing Delay simulations).
Worked on JTAG/P1500 protocols.
Perl/Tcl scripting.
Timing/Formal verification/PD flow knowledge is plus.
Location: Bangalore
Notice Period: Immediate
Experience: 5+ Years
Job Description:
Scan insertion.
SCAN DRC/Coverage debug.
ATPG Pattern generation.
Gate level simulations ( Zero delay/Timing Delay simulations).
Worked on JTAG/P1500 protocols.
Perl/Tcl scripting.
Timing/Formal verification/PD flow knowledge is plus.
Location: Bangalore
Notice Period: Immediate
Experience: 5+ Years
Ready to Apply?
Submit your application today and join our talented team at ALTEN Calsoft Labs.
Submit ApplicationJob Details
- Location Mumbai, Maharashtra
- Job Type Full-time
- Category Engineers
- Posted Date June 09, 2026
- Application Deadline July 19, 2026