Senior/Staff Process Engineer (Wafer Dicing & Back-grind)

• Responsible for silicon photonic wafer backside grinding/thinning process, laser stealth dicing process and die sorting development for silicon photonic chips, with OSAT or internal line.
• Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, edge chipping and optical structure damage of silicon photonic wafers.
• Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.
• Monitor wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.
• Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.
• Compile process SOP, WI, failure repo...

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