Job Description
UST Malaysia in Bayan Lepas, Penang, Malaysia seeks an experienced verification engineer to verify PCIe IP/SoC designs. You will build reusable SystemVerilog/UVM environments, develop directed and constrained-random test cases, and ensure coverage goals are met across Gen3/Gen4/Gen5 PCIe protocols.
Responsibilities include debugging RTL, waveform analysis, and supporting verification closure, while collaborating with design and validation teams to drive sign-off and regression testing.
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Submit ApplicationJob Details
- Location bayan lepas, penang
- Job Type Full-time
- Category Engineering
- Posted Date July 27, 2026
- Application Deadline September 05, 2026