Job Description
Job Summary
Micron Technology is seeking a senior VLSI / Layout Engineer to work on critical IP design and verification in a hybrid location based in Mexico. This role involves working closely with design engineers on floor planning, layout design, and verification protocols in Cadence VLE/VXL and Calibre DRC/LVS environments.
Responsibilities
Use Cadence VLE/VXL and Calibre DRC/LVS to support layout and verification tasks. Collaborate with design engineers to floor plan and design layout. Follow verification protocols and ensure design compliance. Understand and apply tape‐out processes, DFM, and OPC. Document design methodology and interface with design engineers to clarify layout requirements. Organize, prioritize, and manage logistics and resources for project deliverables. Develop methodologies to resolve issues and guide layout designers toward technical and professional development.Requirements
Minimum 6 years of experience with Cadence VLE/V...Ready to Apply?
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Submit ApplicationJob Details
- Location Mexico, jalisco
- Job Type Full-time
- Category Other-General
- Posted Date June 27, 2026
- Application Deadline August 06, 2026