Job Description
A semiconductor company is seeking a skilled Formal Verification Engineer to support their European design teams. The role involves creating and applying formal verification methodologies for complex digital blocks, collaborating closely with design teams, and improving verification flows. Ideal candidates should have experience in ASIC or FPGA development, proficiency in assertion-based techniques, and scripting skills for automation. The position is full-time and can be based in several locations across Europe.
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Submit ApplicationJob Details
- Location reading, england
- Job Type Full-time
- Category Engineering
- Posted Date June 20, 2026
- Application Deadline July 30, 2026