Senior Digital Verification Architect (SystemVerilog/UVM)

Analog Devices
📍 cavite city, cavite, Philippines 💼 Full-time 🕒 Posted June 06, 2026

Job Description

A global semiconductor leader in the Philippines is seeking a Senior Digital Design Verification Engineer to lead verification planning for complex designs. You will architect advanced verification environments and mentor junior engineers while driving innovation in verification approaches. A strong background in SystemVerilog, UVM, and test bench development is required, along with excellent debugging skills. Join a collaborative team dedicated to shaping the future of technology, offering competitive compensation and professional growth opportunities.
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Job Details

  • Location cavite city, cavite
  • Job Type Full-time
  • Category Engineering
  • Posted Date June 06, 2026
  • Application Deadline July 16, 2026