Senior DFT Engineer

Cadence Design Systems, Inc.

📍 ballari, karnataka, India 💼 Full-time 🕒 Posted June 07, 2026

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Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.   
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. 
Must be able to obtain and maintain a Department of Defense classified clearance  
Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) 
Should possess intimate knowledge of DFT insertion flows 
Basic scan chain insertion using synthesis or other software tools Ready to Apply?Submit your application today and join our talented team at Cadence Design Systems, Inc..
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Job Details

Location ballari, karnataka
Job Type Full-time
Category Other-General
Posted Date June 07, 2026
Application Deadline July 17, 2026