Job Description
Job Description1. Develop Die-to-die and UCIe digital IP for HPC SOC.
2. Integration of D2D controller and PHY to timing closure and DFT.
3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation.
4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.Requirement1. Master degree in electrical engineering or computer engineering.
2. 5+ years of experience of digital design and verification.
3. Familiar with digital design and integration flow.
4. Familiar with UCIe standard and design is preferred.
5. Familiar with AMBA protocols and design, particularly AXI and CHI, is preferred.
2. Integration of D2D controller and PHY to timing closure and DFT.
3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation.
4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.Requirement1. Master degree in electrical engineering or computer engineering.
2. 5+ years of experience of digital design and verification.
3. Familiar with digital design and integration flow.
4. Familiar with UCIe standard and design is preferred.
5. Familiar with AMBA protocols and design, particularly AXI and CHI, is preferred.
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Submit ApplicationJob Details
- Location Taiwan, Taipei City
- Job Type Full-time
- Category Engineers
- Posted Date March 02, 2026
- Application Deadline April 11, 2026