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Senior Analog IC Layout Engineer with finFET experience

Chipright
📍 switzerland, switzerland, Switzerland 💼 Full-time 🕒 Posted February 18, 2026
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Job Description

Senior Analog Layout Engineers - 4-5 Engineers 
  • Minimum 7 year's experience in Analog IC Layout
  • Experience working on High Speed Layout
  • Experience working on speeds up to or past 25 Gb/ sec
  • Experience working on finFET technology/ TSMC down to 16nm
  • Experience using Cadence tools

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    Job Details

    • Location switzerland, switzerland
    • Job Type Full-time
    • Category CAR
    • Posted Date February 18, 2026
    • Application Deadline March 30, 2026