Job Description
Exp-5-9yrs
JD:-
- Develop synthesizable RTL code based on micro-architecture and design specifications
- Perform block-level and subsystem-level design and integration
- Work on FSM-based designs, datapath, and control logic implementation
- Collaborate with architecture and verification teams for functional validation
- Debug simulation issues and ensure functional correctness of designs
- Participate in design reviews and documentation of RTL and micro-architecture
- Support synthesis and timing closure activities
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Submit ApplicationJob Details
- Location Bengaluru, Karnataka
- Job Type Full-time
- Category Engineers
- Posted Date July 02, 2026
- Application Deadline August 11, 2026