Job Description
Job Title: RTL Design Engineers Exp Level: 5 yrs Loctaion: Hyderabad/Bangalore Job Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge • Tools knowledge: Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC 0in Formality and conformal LEC tool • Design and scripting languages: Verilog and SV Perl Python TCL
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Submit ApplicationJob Details
- Location Bengaluru, Karnataka
- Job Type Full-time
- Category Engineers
- Posted Date June 04, 2026
- Application Deadline July 14, 2026