Job Description
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Job Description:
This opening work on chip design which enables 10Gbps/40Gbps/100Gbps/400Gbps backplane/cable/optical fiber communication
architect block level design specifications from the marketing requirements and/or system requirements
prepare detailed design document, timing constraint file
HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations & silicon debugging
scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.
prepare block level resource requirements & development schedule
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- Location Irvine, California
- Job Type Full time
- Category Engineers
- Posted Date June 12, 2026
- Application Deadline July 22, 2026