Principal Digital IP Designer

Job Title: Senior RTL Design Engineer (ASIC/SoC)

(with DDR/LPDDR/MIPI exp)

Location: Bangalore, Indi

aExperience: 4+ Year

sNotice Period: 30–45 Days (Preferred

)
Role Overvie

w:We are looking for a highly skilled and motivated ASIC RTL Design Engineer to join our team in Bangalore. You will be responsible for the microarchitecture, design, and implementation of complex digital IP blocks and subsystems. The ideal candidate will have strong expertise in high-speed interface protocols and a proven track record of delivering high-quality RTL within the ASIC/SoC design flo

w.
Key Responsibilit

• iesMicroarchitecture Definit
• ionRTL Implementat

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