Job Description
Job Description1. Power system design architecture (smart phone/automotive)
2. Low power technique development
3. Mixed-signal digital IP design: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs
4. PMIC chip front-end/back-end integration
#LI-DC3
Requirement1. Experience: 3+ years
2. Familiar with Verilog HDL, digital design flow and related CAD tools
3. Digital/analog interface spec./design experience (nice to have)
4. Chip tapeout experience, and MP experience (nice to have)
2. Low power technique development
3. Mixed-signal digital IP design: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs
4. PMIC chip front-end/back-end integration
#LI-DC3
Requirement1. Experience: 3+ years
2. Familiar with Verilog HDL, digital design flow and related CAD tools
3. Digital/analog interface spec./design experience (nice to have)
4. Chip tapeout experience, and MP experience (nice to have)
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Submit ApplicationJob Details
- Location Hsinchu City, Taiwan Province
- Job Type Full-time
- Category Engineers
- Posted Date February 21, 2026
- Application Deadline April 02, 2026