Job Description
Mixed Signal Design Verification Engineer
Salary: Very Attractive Rate
Location: N/A
Mixed Signal Design Verification Engineer
- Implementation of System Verilog Models for the Analog blocks
- Model vs Schematic Verification – System Verilog Test bench implementation including assertions
- Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
- Understanding of UVM environment and implementing the Top Level Test cases in the environment
- Running regressions using VManager
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Submit ApplicationJob Details
- Location , , United Kingdom, , , United Kingdom
- Job Type Full-time
- Category Engineering
- Posted Date March 02, 2026
- Application Deadline April 11, 2026