Memory Layout Engineer

• Experience : 3 to 8 years
• Location : Hyderabad/Noida

Role and Responsibilities:

• Responsible for Memory Compiler layout development and verification.·
• Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·
• Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· Responsible for on-time delivery of block-level layouts with acceptable quality.· Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.·
• Guide junior team-members in their execution of Sub block-level layouts & review their work.·
• Contribute to effective project-management.·
• Effectively communicate with engineering teams in the India & Korea teams ...

Ready to Apply?

Submit your application today and join our talented team at ACL Digital.