Lead design verification engineer

Lead Design Verification Engineer
Location: Bengaluru
Experience: 6–12 Years
Role Overview
Lead Soc Technologies is seeking a highly skilled Lead Design Verification Engineer to drive verification of next-generation So C/IP designs. The ideal candidate will possess deep expertise in high-speed protocols, RISC-V architecture, computer architecture concepts, and advanced System Verilog/UVM-based verification methodologies.
Key Responsibilities
Lead verification activities for complex So C, subsystem, and IP-level designs from specification to tape-out.
Develop comprehensive verification plans, testbench architectures, coverage models, and verification strategies.
Build and maintain scalable verification environments using System Verilog and UVM.
Verify RISC-V processor cores, cache subsystems, interconnects, and So C fabrics.
Develop constrained-random, directed, and scenario-based test suites to achieve coverage closure.
Perform protocol compliance and i...

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