At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Responsibilities:
The Candidate will have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure. Physical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools Physical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE, etc and test chips for advanced process nodes, such as 7nm/5nm/3nm/2nm An opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs. Work closely with RTL design team & Analog Team to ensure on-time, successful tapeou...