interconnect fabric design and system level cache IP engineer

Job Description1. Interconnect IP/Fabric IP/System-level-cache IP/related bus-subsys design for different products (smartphone/AUTO/...)
2. Cowork with DV team to secure functionality
3. Cowork with performance validation team to secure performance requirement (BW/latency) is met
4. IP Design Quality Control flow execution (lint, CDC, spyglass DFT, UPF,...)
5. RTL Front-End flow execution (SDC quality check, clock constraint check, ...)

#LI-LL1Requirement1. Familiar with digital IC design, DFT flow
2. Experienced in SoC architecture, and bus (AMBA bus) spec is a plus
3. Experienced in chip integration is a plus
4. Experience with External Memory Interface design is a plus
5. Experience with DV verification job is a plus
6. Experience with security hardware design is a plus
7. Experience with performance (BW/Latency) analysis is a plus
8. Programming skills in C/Python
9. Good written and oral communication skills
10. Str...

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