Job Description
Job Description
Job Description: This role is for a mid-level FPGA/Firmware Engineer involved in the redevelopment of a flagship product. Responsibilities include VHDL code development, interface control between the FPGA and Digital-to-Analog Converters (DAC) or Analog-to-Digital Converters (ADC), IO control in reference to aircraft systems, and providing documentation to support certification (DO-254). The role focuses on integrating commercial off-the-shelf FPGAs (e.g., Xilinx) and writing VHDL for interfaces and I/O.
Location: Willingness to work onsite 5 days a week in Phoenix, AZ (Grand Rapids, MI as a secondary option, St, Pete Florida as 3rd).
Schedule: 980
Top 1-2 Priorities this role will be expected to deliver within the first 90 days:
1. Program Execution & Code Development: Immediately contribute to VHDL code development or interface control between FPGAs and converters, with a focus on active design work for the current program.
2. Proce...
Job Description: This role is for a mid-level FPGA/Firmware Engineer involved in the redevelopment of a flagship product. Responsibilities include VHDL code development, interface control between the FPGA and Digital-to-Analog Converters (DAC) or Analog-to-Digital Converters (ADC), IO control in reference to aircraft systems, and providing documentation to support certification (DO-254). The role focuses on integrating commercial off-the-shelf FPGAs (e.g., Xilinx) and writing VHDL for interfaces and I/O.
Location: Willingness to work onsite 5 days a week in Phoenix, AZ (Grand Rapids, MI as a secondary option, St, Pete Florida as 3rd).
Schedule: 980
Top 1-2 Priorities this role will be expected to deliver within the first 90 days:
1. Program Execution & Code Development: Immediately contribute to VHDL code development or interface control between FPGAs and converters, with a focus on active design work for the current program.
2. Proce...
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- Location Phoenix, AZ
- Job Type Full-time
- Category other-general
- Posted Date June 27, 2026
- Application Deadline July 02, 2026