Job Description
Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. Should be an enthusiastic and a quick learner of the verification flow. Job Description: SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Experience with python or any other scripting language is a plus Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Experience: 4 to 6 Years Location: Hyderabad
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Submit ApplicationJob Details
- Location Hyderabad, Telangana
- Job Type Full-time
- Category Engineers
- Posted Date July 03, 2026
- Application Deadline August 12, 2026