Formal verification engineer

Minimum Qualification:
Bachelor's/ Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3-10 years of experience with formal verification ASIC design.
Experience writing formal properties using System Verilog Assertions (SVA).
Experience with EDA tools (e.g., Jasper Gold, Questa Formal, VC Formal
Preferred qualifications:
Master's degree or Ph D in Electrical Engineering or Computer Science.
Experience with scripting languages.
Knowledge of specific formal applications, abstraction techniques and proof convergence strategies.
Responsibilities:
Develop formal verification test plans to verify digital hardware designs.
Work cross functionally with teams to analyze specifications and resolve bugs.
Drive improvements to formal verification methodologies to enhance quality and efficiency.

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