Job Description
Job DescriptionMediaTek Chip Physical Verification team is looking for qualified candidate to be part of a team that define and enable physical sign-off flow and solutions for SOC design. The candidate will be enabling technology in advanced technology nodes.
• Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
• Co-work with Place & Route team to resolve full-chip layout integration issues.
• Coordinates with internal IP owners on IP related issues.
• Coordinates with Manufacturing Team on DRC related issues.
• Provide automation solutions to improve efficiency in tape-out flow.
• Report on tapeout PV issues.
#LI-WC1Requirement• Bachelor/master’s degree in electrical/Electronic Engineering/Computer Science
• Familiar with IC Design front-to-backend flow
• Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
• Proficient in script programming, such as Python, TCL, Perl,...
• Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
• Co-work with Place & Route team to resolve full-chip layout integration issues.
• Coordinates with internal IP owners on IP related issues.
• Coordinates with Manufacturing Team on DRC related issues.
• Provide automation solutions to improve efficiency in tape-out flow.
• Report on tapeout PV issues.
#LI-WC1Requirement• Bachelor/master’s degree in electrical/Electronic Engineering/Computer Science
• Familiar with IC Design front-to-backend flow
• Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
• Proficient in script programming, such as Python, TCL, Perl,...
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Submit ApplicationJob Details
- Location Singapore, Singapore
- Job Type Full-time
- Category Engineers
- Posted Date June 17, 2026
- Application Deadline July 27, 2026