Job Description
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Job Description:
1.Participate in chip level DFT architecture definition.
2.Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
3.Verify all DFT logics and test patterns with simulation
4.Test modes static timing analysis
5.Participate in ATE bring-up and debug the DFT patterns on ATE.
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- Location Pu Dong Xin Qu, Shang Hai Shi
- Job Type Full-time
- Category Engineers
- Posted Date June 07, 2026
- Application Deadline July 17, 2026