Home / Jobs / Design For Test Engineer (Einfochips Inc)

Design For Test Engineer (Einfochips Inc)

eInfochips, Inc
📍 Mountain View, California, United States 💼 Full time 🕒 Posted June 10, 2026
Apply Now Similar Jobs

Job Description

Description

What You'll Be Doing:

  • DFT implementation for 3nm and 5nm Networking chips, IP DFT work

  • RTL checks for scan-insertion compatibility using Synopsys Spyglass

  • Scan-Insertion using Tessent TestKompress

  • ATPG pattern generation:

  • Compressed and Uncompressed Mode

  • Mentor Tessent, Cadence Modus & Synopsys Tetramax

  • Pattern Simulation:

  • Without timing, With timing for different corners

  • VCS

  • Mismatch debug using

  • Scripting with Perl, Shell, TCL:

  • DAeRT - DFT flow enhancement/automation in project

  • Makefile enhancement using extended scripts and targets for flow enhancement

  • MBIST Insertion and Verification:

  • MBIST Insertion and Verification done on block on top

  • Silicon debug and bring-up done for block and top

  • IEEE ...

    • Ready to Apply?

    Submit your application today and join our talented team at eInfochips, Inc.

    Submit Application

    Job Details

    • Location Mountain View, California
    • Job Type Full time
    • Category Engineers
    • Posted Date June 10, 2026
    • Application Deadline July 20, 2026