Job Description
This role serves as a core technical leader responsible for end‑to‑end defect engineering—from advanced SiC defect reduction and AI‑based inspection operations to SPC‑driven yield and reliability improvement—bridging UPS, Defect Management, and Fab organizations from technology development through mass production.
Key Responsibilities & Scope
(1) SiC Technology Advancement and New Defect Mode Improvement
SiC MOSFETs, Super Junction structures, multi‑epitaxial growth, and Trench Gate devices
(2) ADC & Klarity Operation and Production / VOG Management
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Submit ApplicationJob Details
- Location Bucheon-si, Gyeonggi-do
- Job Type Full time
- Category Engineers
- Posted Date June 05, 2026
- Application Deadline July 15, 2026