Job Description
Experience: 10+ Years
Employment Type: Full-Time
Job Summary
We are seeking a highly experienced Senior DFT Engineer with strong expertise in Path Delay Fault (PDF) pattern generation, STA timing analysis, and silicon debug activities. The ideal candidate should be fully independent, self-driven, and capable of owning the complete DFT path delay fault flow from pattern generation to coverage improvement and silicon validation.
Key Responsibilities
- Develop and generate Path Delay Fault (PDF) ATPG patterns using Siemens Tessent tool chain.
- Analyze and interpret STA timing reports to identify critical and timing-marginal paths.
- Perform path selection, timing-aware ATPG, and pattern validation for high-speed designs.
- Debug and improve path delay fault coverage through detailed analysis and optimization techniques.
- Work closely with design, STA, physical design, and validation tea...
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Submit ApplicationJob Details
- Location kuala lumpur, kuala lumpur
- Job Type Full-time
- Category Management & Operations
- Posted Date June 06, 2026
- Application Deadline July 16, 2026