Job Description
Etteplan is seeking a Chief/Lead FPGA Engineer to oversee FPGA architecture and development. The role emphasizes technical leadership and involvement in all stages of the FPGA development lifecycle.
Applicants should have 10-15+ years of FPGA design experience, proficiency in VHDL/SystemVerilog, and strong communication skills in Finnish and English. We offer a collaborative environment and competitive compensation.
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Submit ApplicationJob Details
- Location espoo, uusimaa
- Job Type Full-time
- Category Design & Development
- Posted Date June 21, 2026
- Application Deadline July 31, 2026