Job Description
Position: ASIC RTL Design Engineer
Experience: 8+ Years
Location: Noida
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Key Responsibilities
Develop synthesizable RTL from micro-architecture specifications. Design digital blocks such as control logic, datapath, and bus interfaces (AXI/AHB/APB). Debug and validate RTL using simulation and waveform analysis. Collaborate with verification teams for functional validation. Support RTL synthesis, timing closure, and integration at So C level. Maintain design documentation.Required Skills
Strong digital design fundamentals. Experience in Verilog/System Verilog RTL coding. Knowledge of AMBA protocols (AXI/AHB/APB). Familiarity with synthesis, lint, and CDC tools.Good debugging and problem-solving skills.
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Submit ApplicationJob Details
- Location noida, uttar pradesh
- Job Type Full-time
- Category Other-General
- Posted Date June 06, 2026
- Application Deadline July 16, 2026