Job Description
CERN designs, develops, and operates particle accelerators and experiments. You will join the HSE-TS-IMS Section to design, verify, and bring up the next-generation ASIC front-end using open-source EDA tools, with a focus on RTL to GDSII work.
The role involves collaboration across SoC, analogue, and verification teams in a hybrid work setting. Requirements include hands-on experience with Yosys/OpenROAD/LibreLane, RTL design in Verilog/SystemVerilog, and knowledge of RISC-V.
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Submit ApplicationJob Details
- Location genf, genf
- Job Type Full-time
- Category Other-General
- Posted Date July 28, 2026
- Application Deadline September 06, 2026