ASIC Design for Testability Engineer, Silicon

ASIC Design for Testability Engineer, Silicon

_corporate_fare_ Google _place_ Bengaluru, Karnataka, India

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience.
+ 4 years of experience in DFT/DFD flows and methodologies.
+ Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow.
+ Experience with DFT EDA Tool Tessent/Genus/FC/Simvision etc.

**Preferred qualifications:**

+ Experience with DFT for a Complex subsystem with multiple physical partitions.
+ Experience with IJTAG ICL, PDL...

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