Job Description
Analog Layout EngineerJob description: Experience in manual full-custom Analog layout of IC in CMOS/Bi-CMOS process. Experience with high frequency layout design verification and debugging such as DRC, ERC, ESDDRC, LVS, ANTENNA DRC, using verification tool such as PVS. Floor planning from sub-block to chip top level Very organized and result oriented Very good understanding of matching techniques
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- Location france, france
- Job Type Part Time
- Category Engineers
- Posted Date June 25, 2026
- Application Deadline August 04, 2026