Job Description
Chipright seeks highly motivated and experienced Analog Layout development engineer to work on Memory IP’s.
• 7+ years’ minimum experience in Physical layout
• Experience working with Memory IPs, and top level layout of test chips
• Proficient with Cadence design and layout environment
• Coordinate Tapeout procedure for internal and external Foundries
• Main layout focus: Memories and Supporting Blocks, ADC/DAC, Testchip placement
• Knowledge of LayoutXL, Calibre/Assura is a plus
• Adapt IP blocks and support integration into key projects
• Strong communication with all necessary interfaces like Process Development, Design, Test Development, Production, Quality
Chipright –
• 7+ years’ minimum experience in Physical layout
• Experience working with Memory IPs, and top level layout of test chips
• Proficient with Cadence design and layout environment
• Coordinate Tapeout procedure for internal and external Foundries
• Main layout focus: Memories and Supporting Blocks, ADC/DAC, Testchip placement
• Knowledge of LayoutXL, Calibre/Assura is a plus
• Adapt IP blocks and support integration into key projects
• Strong communication with all necessary interfaces like Process Development, Design, Test Development, Production, Quality
Chipright –
Ready to Apply?
Submit your application today and join our talented team at Chipright.
Submit ApplicationJob Details
- Location Austria, Austria
- Job Type Part Time
- Category Engineers
- Posted Date February 28, 2026
- Application Deadline April 09, 2026